The prior art teaches the formation of integrated circuits which utilize one or more FinFET type field effect transistors. The FinFET transistor comprises a channel region which is oriented to conduct an electrical current parallel to the surface of the substrate. The channel region is provided in an elongated section of semiconductor material referred to as a fin. The source and drain regions of the transistor are typically also formed in the elongated section on either side of the channel region. A gate is placed over and on both opposed sides of the elongated section at the location of the channel region to provide control over the conductive state of the transistor. This FinFET design is well suited for manufacturing a multi-channel transistor in which multiple elongated sections are formed in parallel to define neighboring channel regions which are separated from each other by an intermediate gate portion of the transistor gate spanning with a perpendicular orientation over the multiple elongated sections.
The fin of a FinFET transistor is typically defined by a mask that is formed on top of a monocrystalline silicon substrate at the position of the fin. The substrate material is then directionally etched where there is no mask, to a determined depth, such that the elongated section defining the fin remains under the mask and is composed of the substrate material. It is desirable to insulate the fin from the active portion of the circuit substrate in order to address concerns with leakage currents.
For fabrication of a FinFET on a bulk substrate, several techniques are known for fabricating an insulating oxide underneath the fin. For example, in the known bottom oxidation through STI (BOTS) technique, barriers are formed on either side and on top of the fin. The integrated circuit wafer is then subjected to an oxidation process which converts a lower portion of the fin, which is not protected by the barriers, to an insulating thermal oxide material which isolates the upper portion of the fin from the underlying substrate material. In another technique, referred to in the art as the silicon on nothing (SON) technique, a bottom portion of the fin formed from silicon-germanium is selectively etched to produce an open region. The open region is then filled with an insulating dielectric material to isolate the fin from the substrate.
With respect to fabrication of a FinFET on a silicon on insulator (SOI) substrate, the fin is patterned in a top semiconductor (for example, silicon or silicon-germanium) layer positioned over an insulating (for example, silicon dioxide) layer located over a bottom semiconductor (for example, silicon) substrate layer. The insulating layer serves to insulate the fin from the bottom semiconductor substrate layer. Reference is made to U.S. Pat. No. 6,645,797, the disclosure of which is incorporated by reference, which teaches a process for realizing a FinFET transistor from an SOI substrate where the fin is electrically insulated from the lower part of the substrate by the intermediate layer of insulating material.
It is also known in the art to form a FinFET transistor with only a partial dielectric isolation of the fin. In this regard, the fin is considered to be partially isolated when only the channel portion of the fin (under the gate) is isolated from the underlying substrate but the source-drain regions are otherwise in contact with the substrate. To achieve this structure, the prior art teaches the removal of the insulated fin material outside of the channel region associated with the overlying gate and then performing a subsequent regrowth, for example using epitaxy, of semiconductor material on either side of the gate to define source and drain regions. The advantage of this fabrication technique is that the epitaxially grown source and drain regions on either side of the gate can add stress to the channel region formed by the fin. However, because these source and drain regions are in contact with the underlying substrate and spread beyond the area occupied by the fins, there is a large surface area through which current leakage to the underlying substrate can occur.
There is accordingly a need in the art, when fabricating FinFET devices with partially isolated fins, to provide for control over the epitaxially grown source and drain regions so as to reduce the area of substrate contact.